An Analogue VLSI Morphological Image Processing Circuit

We present an analogue VLSI circuit that performs morphological image processing operations on the focal plane. The circuit has been fabricated using a standard digital CMOS process. We exploit the parallelism of morphological image processing operations by using the massively parallel architecture of analogue VLSI arrays, achieving both high-speed and low-power computation [1]. The analogue circuit presented computes the grey-scale morphological operation of dilation. This system also allows for programmability of the structuring element used in the dilation operation. Introduction Mathematical morphology is a nonlinear image processing approach that uses set theory to perform functions such as object detection and image segmentation [2][3]. We have developed analogue VLSI circuits that perform the primary operations of morphological image processing [4][5]. These circuits exploit the parallelism of morphological image processing operations by using 2-dimensional arrays of smart pixels that collectively receive and process parallel input data to compute a parallel array of outputs in real time. Focal-plane morphological image processing systems have already been implemented using digital computation on a binary image [6]. Our design makes use of analogue circuitry for the processing of grey-scale images. In this paper, we present one example system that computes the dilation of an image with a choice of structuring elements, and also computes the difference between the dilation and the original image to detect edges. The dilation operation uses a mask-like filter, called a structuring element, to determine the spatial extent and orientation of its nonlinear computation. For the circuits that we have developed, we use binary structuring elements that include any combination of pixels within a 3 x 3 mask. Circuit Description The dilation of a grey-scale image by the structuring element can be computed by the following expression: { | ∀ (i,j) ∈B}, (1) where is the dilated output image, and the symbol denotes the dilation operator. The dilation operation is performed at each location of the array, where the mask, called a structuring element, determines which inputs are included in the maximum computation. The structuring element is determined through the local communication of neighboring pixel values in the computation of the maximum at each output location. The dilation system that we present allows for a programmable structuring element by choosing a combination of any of the eight neighbors, including diagonal neighbor pixels, in addition to the central pixel. Each pixel is composed of a photodetector and processing circuitry that receives inputs from neighboring pixels in order to compute the dilated output for that location. Beyond the task of duplicating signals for the local communication, each pixel houses circuitry to compute the maximum of the nine inputs that are included in the structuring element set, thus computing the dilation at that location. Figure 1 shows the circuitry for each pixel in the dilation processing array, consisting of a vertical bipolar photodetector, a current mirror to duplicate the photocurrent, and switches to control outputs and local communication. (The switches are programmed with binary inputs, indicated in the figure by the values.) The voltages CT1 and CT2 multiplex the output currents to read the input value, dilation value, or the point-wise difference between the input and dilation values. The maximum circuit is a modification of a current-mode winner-take-all circuit [7] that compares a number (in this case, nine) of input currents and duplicates the maximum input current as its output current. The maximum circuit, also shown in Figure 1, is an array of identical processing elements, each of which consists of two transistors. One of these transistors (the input transistor) sinks the input current that corresponds to its element. The input transistors of all of the elements share a common gate voltage . This voltage must be large enough to allow the largest input current to be sunk when its corresponding transistor is saturated, and thus encodes the maximum input current. The maximum input current is then replicated by using a transistor that has as its gate voltage. Assuming that this transistor is saturated and is the same size as the individual input transistors, the output current generated by this transistor will be identical to the maximum input current (modulo drain resistance and device mismatch). X m n ( , ) B m n ( , ) YD m n ( , ) X B ⊕ ( ) m n ( , ) max = = X m i + n j + ( , ) YD m n ( , ) “ “ ⊕